Field of the Invention
The present invention is related to a stacked multilayer structure, a manufacturing method thereof, and a semiconductor device using said stacked multilayer structure.
Description of the Related Art
The demand for miniature and large capacity nonvolatile semiconductor devices is increasing. In order to realize this miniaturization and large scale capacity, a number of devices in which semiconductor elements such as memory cell transistors are arranged three dimensionally have been proposed. For example, such devices are disclosed in the United States Patent Publication No. US-20020154556-A1, the U.S. Pat. No. 5,599,724, No. U.S. Pat. No. 5,707,885, and Masuoka et al, “Novel Ultrahigh-Density Flash Memory With a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell” IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 50, N04, pp 945-951, April 2003.
In such devices in which semiconductor elements and the like are arranged three dimensionally, a plurality of conducting layers are stacked to form a stacked multilayer structure, each of said plurality of conducting layers being connected to several electrodes of said elements positioned on the same layer. And there is a need to connect each of said plurality of conducting layers to a driving circuit. Thereupon, there is a need to form efficiently these connection structures while keeping their reliability.